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Re: [Xylo-SDR] Latest S3 ADC schematic
----- Original Message -----
From: "Phil Harman" <email@example.com>
To: "Xylo-SDR Discussion" <firstname.lastname@example.org>
Sent: Monday, January 02, 2006 2:15 AM
Subject: Re: [Xylo-SDR] Latest S3 ADC schematic
Thanks for posting your latest circuit. You may need to pass the 24.576MHz
clock across to your FPGA. That is unless you know a way of running with
it - in which case please let the rest of us know how!
Presently Bill and I are using two state machines in the FPGA - one runs
the 24.576MHz clock and talks to the A/D converter and the other off the
clock (12/24/48MHz) and talks to the FX2. The FX2 USB connection appears
be very unforgiving if you don't use its clock for any USB associated
I was intending to make the ADC interface asynchronous. Do you think I'll
have a problem? I'll add the connection, just in case.