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Re: [Xylo-SDR] Janus board block diagram
Attached is my V1.0 block diagram of the A/D and D/A board in both
Visio and HTML format. I've called this "Janus" after the Roman god of
gates and doors (ianua), beginnings and endings, who could see both ways
at once ( input and outputs :) ).
I've drawn the block diagram for the Wolfson A/D but it much the same
for the others. The PCM4202 is does not have an I2C interface to set it
up so we either uses jumpers, FPGA pins or an I2C I/O port etc.
Fortunately there are only a few pins that need to be configured. IF
you have the pins available, the FPGA is more flexible. Otherwise,
jumpers work pretty well :-)
A few questions:
Should we use the TLV320's 30mW audio amplifiers instead of the PWM
A/D'S for our audio output? That way you could connnect a pair of
headphones directly to the card. Disadvantage is that we are then
relient on the TI chip in the future.
The amps are already there and work pretty well. The Janus board relies
on the TI chip already; if the chip goes away, the board has to be re-done.
Given that D/A's are very easy to implement in the FPGA should we add a
few more for control of external equipment e.g. an external linear
The TLV320 needs to run at (24.576/2)MHz - should we derive this from
the FPGA or add a divide by 2 to the board so this clock does not need
to pass back over the back plane?
Given that the 24 MHz clock is already being passed over the backplane,
bringing the 12 MHz clock back shouldn't affect things too much (noise,
etc.). OTOH, a 74LVC74 is dirt cheap :-)