Re: [Xylo-SDR] Signal Integrity and Board stackup issues

["Ray Anderson" <ray.anderson@xilinx.com>]

Eric-

Whenever an interconnect must be considered a 'transmission line' (i.e.
when the time delay of the line is greater than about 20% of the signal
risetime) then it is generally necessary to terminate the line to
control reflections.

For the case of boards with FR4 dielectric (where the Er is approx 4 and
signals travel at about 6 inches/nsec) the above can be simplified to
produce a rule-of-thumb that says that termination is required when the
line length (in inches) is > than the risetime (in nsec).

So for a typical FPGA driver (say LVDS) that has a risetime of about
350psec  (.35nsec) then for lines greater than about a third of an inch
you should utilize termination.

For slow risetime signals the line can be correspondingly longer before
termination becomes an issue. A 10MHz clock signal with a 10nsec
risetime wouldn't require termination for line lengths less than about
10 inches.

The USB signals have a risetime speced as > 500psec I believe. So lines
over about a half an inch will need termination. (the standard defines
recommended schemes I believe)


Fast I2C specs the ristime at about 300nsec so termination isn't an
issue for lines less than 25 feet. (though there other issues to be
considered)

 
The simplest termination scheme is a resistor of the appropriate value (
Zo) at the far end of the transmission line. For differential lines
(LVDS) the termination scheme is a bit more involved since you need to
terminate both the even and odd modes (this takes 3 resistors).
Resistive terminations dissipate power. If this is an issue the addition
of an appropriately selected capacitor provides the benefits of AC
termination with no DC power being consumed. Some busses can benefit
from series termination, but there are other considerations for this
scheme.

So what's the downside from not terminating a line? Basically you can
multiple reflections (standing waves) bouncing back and forth on the
line adding noise, trashing your signal, causing unwanted data
transitions and all others sorts of undesirable effects.


I'll take a look at the posted documentation and block diagrams and see
if I can come up with a simple set of design rules.


-Ray  WB6TPU


-------------Begin Original Message----------------
Message: 4
Date: Wed, 25 Jan 2006 21:34:51 -0500
From: "Eric Ellison" <ecellison@comcast.net>
Subject: Re: [Xylo-SDR] Signal Integrity and Board stackup issues
To: "'Xylo-SDR Discussion'" <xylo-sdr@lists.ae5k.us>
Message-ID: <006301c62221$19df0830$7501a8c0@Development>
Content-Type: text/plain;	charset="us-ascii"

Ray

Can you tell me anything about the art of termination, do we need it?
What
lines?

Eric


---------------End Original Message-----------------