Difference between revisions of "EPIMETHEUS"
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The project leader for EPI is Phil VK6APH. | The project leader for EPI is Phil VK6APH. | ||
| − | Epimetheus (or Epi for short) is a general purpose input/output board that sits on the Atlas bus. | + | [[Image:Epi V1.0.jpg|thumb|500px]] |
| + | '''Epimetheus''' (or Epi for short) is a general purpose input/output board that sits on the Atlas bus. | ||
Early days as yet but the following block diagram explains the concept: | Early days as yet but the following block diagram explains the concept: | ||
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The design will use a CPLD written by Steve KA6S consisting of an I2C slave, I2C master (from OpenCores), and a micro-coded Wishbone Master that is capable of sending messages over the I2C Master. | The design will use a CPLD written by Steve KA6S consisting of an I2C slave, I2C master (from OpenCores), and a micro-coded Wishbone Master that is capable of sending messages over the I2C Master. | ||
| − | [[Image:epi_block_v0.1.jpg]] | + | [[Image:epi_block_v0.1.jpg|thumb|500px]] |
The I2C Slave is used to program all on-chip resources including uploading the Wishbone Master Microcode, and initializing the device control registers and I2C master. | The I2C Slave is used to program all on-chip resources including uploading the Wishbone Master Microcode, and initializing the device control registers and I2C master. | ||
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It is intended that the configuration be done via a GUI running on the PC. | It is intended that the configuration be done via a GUI running on the PC. | ||
| − | The Verilog Code specification is found in | + | The Verilog Code specification is found in [[media:epi_cpld_v0.1.pdf|epi_cpld_v0.1.pdf]] |
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Any ideas/suggestions/requests for other I/O that we can put on the board? | Any ideas/suggestions/requests for other I/O that we can put on the board? | ||
Revision as of 03:26, 1 June 2009
The project leader for EPI is Phil VK6APH.
Epimetheus (or Epi for short) is a general purpose input/output board that sits on the Atlas bus.
Early days as yet but the following block diagram explains the concept:
The design will use a CPLD written by Steve KA6S consisting of an I2C slave, I2C master (from OpenCores), and a micro-coded Wishbone Master that is capable of sending messages over the I2C Master.
The I2C Slave is used to program all on-chip resources including uploading the Wishbone Master Microcode, and initializing the device control registers and I2C master.
The micro-coded Wishbone Master watches for changing inputs (button pushes) and will send a message to system controller (Ozy) via I2C with the new button port data. This allows Ozy to be informed of button pushes without Ozy having to constantly poll the Epi board.
There are two separate I2C ports. These are intended to be tied together externally onto a single I2C bus.
The Epi Control registers control all of the output pins, and are used to control the external switch matrix.
The use of a CPLD rather than a uP should result in an EMC quieter solution. The 200MHz cross point switch is intended for use with VHF/UHF/SHF transverters so that the various IFs can be switched around. The switches are intended to handle a few 10?s of mW so can be used to switch low level HF/2m etc drive around.
Since we can control the switching functions via USB from the PC we can include all manner of sequencing etc for amplifiers, preamps etc.
It is intended that the configuration be done via a GUI running on the PC.
The Verilog Code specification is found in epi_cpld_v0.1.pdf
Any ideas/suggestions/requests for other I/O that we can put on the board?
Why Epimetheus? From Encyclopedia Mythica? "Epimetheus ("afterthought") is the son of Iapetus and Clymene. He foolishly ignored his brother Prometheus' warnings to beware of any gifts from Zeus*. He accepted Pandora as his wife, thereby bringing ills and sorrows to the world".
Well the afterthought bit fits but I sure hope the latter doesn't!
(*you know what I mean Bob!)
