Difference between revisions of "Phoenix Schematics"
(New page: The '''Interface Circuit''' uses a small CPLD as in the other HPSDR modules to map to the bus in a programmable way. It will also allow experimentation with various clock schemes. The '''...) |
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| − | + | '''Schematics''' | |
| − | The | + | The root sheet schematic [[Image:Root_sheet.gif]] gives an idea of the overall layout. |
| − | The '''Mixer/QSD''' is based on various comments and sources.It uses the devices proposed originally. | + | |
| + | |||
| + | '''Interface Circuit''' | ||
| + | [[Image:Interface.gif]] | ||
| + | |||
| + | The interface Circuit uses a small CPLD as in the other HPSDR modules to map to the bus in a programmable way. It will also allow experimentation with various clock schemes. | ||
| + | |||
| + | |||
| + | |||
| + | '''DDS circuit''' | ||
| + | [[Image:DDS.gif]] | ||
| + | The DDS circuit uses the latest device from Analog Devices - the AD9912. This has better SFDR and output freq range than previous devices. I have elected to use a PECL driver for the CPLD and a packaged LPF for convenience. | ||
| + | |||
| + | |||
| + | The DDS requires several regulators for best performance. [[Image:DDSpower.gif]] | ||
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| + | |||
| + | |||
| + | '''Mixer/QSD'''[[Image:receiver.gif]] | ||
| + | The Mixer/QSD is based on various comments and sources.It uses the devices proposed originally. | ||
The CPLD will be used to generate quadrature signals from the DDS. No preamp/filters have been included at this stage. | The CPLD will be used to generate quadrature signals from the DDS. No preamp/filters have been included at this stage. | ||
| − | |||
| − | Note | + | |
| + | '''QSE''' [[Image:QSE.gif]] | ||
| + | The QSE circuit is basically the reverse of the receiver with a low level power amp | ||
| + | |||
| + | |||
| + | Note there is no DDS clock circuit at this point. This is still under development, though a simple crystal oscillator module will be used for prototypes. | ||
Revision as of 04:52, 22 January 2008
Schematics
The root sheet schematic 
gives an idea of the overall layout.
Interface Circuit
The interface Circuit uses a small CPLD as in the other HPSDR modules to map to the bus in a programmable way. It will also allow experimentation with various clock schemes.
DDS circuit
The DDS circuit uses the latest device from Analog Devices - the AD9912. This has better SFDR and output freq range than previous devices. I have elected to use a PECL driver for the CPLD and a packaged LPF for convenience.
The DDS requires several regulators for best performance. 
Mixer/QSD
The Mixer/QSD is based on various comments and sources.It uses the devices proposed originally.
The CPLD will be used to generate quadrature signals from the DDS. No preamp/filters have been included at this stage.
QSE 
The QSE circuit is basically the reverse of the receiver with a low level power amp
Note there is no DDS clock circuit at this point. This is still under development, though a simple crystal oscillator module will be used for prototypes.
