Phoenix Schematics

The Interface Circuit uses a small CPLD as in the other HPSDR modules to map to the bus in a programmable way. It will also allow experimentation with various clock schemes.

The DDS circuit uses the latest device from Analog Devices - the AD9912. This has better SFDR and output freq range than previous devices. I have elected to use a PECL driver for the CPLD and a packaged LPF for convenience.

The Mixer/QSD is based on various comments and sources.It uses the devices proposed originally. The CPLD will be used to generate quadrature signals from the DDS. No preamp/filters have been included at this stage.

The QSE is similar setup in the opposite direction.

Note that there is no DDS clock circuit at this point. This is still under development, though a simple crystal oscillator module will be used for prototypes.