(more info and documentation coming here)
FPGA Programming: Verilog & VHDL
Which is best? Verilog or VHDL?
The question was asked recently on our HPSDR Discussion List about Verilog versus VHDL and which was more user friendly. In response to this query, Rick Eversole, N6RNO, gave this reply:
(Reprinted here by permission of the author)
Yet another answer from one who has used both languages for 17 years. I have worked for Cadence, Mentor Graphics and now Synopsys. I get paid to know both languages. I have written thousands of lines of code in both. I know 29 programming languages (including Verilog and VHDL). I prefer Verilog and in recent years it appears that VHDL is finally falling behind.
While Verilog is being upgraded to "SystemVerilog", the VHDL camp is finding it hard to find funding to update the latest LRM. "SystemVHDL" may not actually be needed but as it stands now I do not think it will ever happen.
Verilog is C-like (Prahbu Goel and Phil Morby [creators of the language] liked C). Not strongly typed. Subject to coded race conditions. But fastest to learn and tuned toward hardware better than VHDL. Verilog simulates faster than VHDL. Verilog has gate level primitives (AND, NAND, NOR etc) as part of VHDL. A useful value type system is part of base Verilog.
VHDL is based upon ADA (Many of the same people who specified the ADA language were involved in the creation of VHDL). It is a strongly typed language. It is very hard to code a race condition. It takes longer to learn. More typing is involved to accomplish the same task in VHDL as compared to Verilog. VHDL simulates slower than VHDL (2-4x slower is typical even for gate level simulations). VHDL does not have gate primitives. You have to code them in RTL style.
The "VITAL" specification provides a set of gate primitves that map to Verilog primitives. VHDL does not have a logic system that is useful for gate designs. You need the "standard logic 1164" package which ships with any real VHDL simulator. Like Vital this is a layer on top of the base language.
Over the years I have seen side by side test with "expert" VHDL users and Verilog users. In general the Verilog users out perform the VHDL users. There are lots of issues with how these tests are constructed but my experience shows that Verilog is fasest to get the design done but VHDL designs often are easier to maintain and update.
Each language has advantages. The new SystemVerilog language will remove all but VHDL's strong typed "advantage". Whether strongly typed is a real advantage is a debate for another time.
In practice, it is not possible to translate between the languages. Semantics are incompatible. You have to completely recode in a non-mechanical process. Translators can help but 30% recode is not uncommon. (unless you have pure structural code then translation can be almost 100%).
--Rick "The Rhino" N6RNO
Tutorial Resources for Verilog
Tutorial Resources for VHDL
Good Reading Link
GNU Radio has a nice page with a lot of good reference reading information on it. http://gnuradio.org/trac/wiki/SuggestedReading
Here's a link to one possible VERY SMALL power supply for the Atlas backplane: http://www.mini-box.com/s.nl/it.A/id.417/.f?sc=8&category=13
Please note that extensive testing has not been performed yet on this unit and as of this writing it is not in stock. The HPSDR group does not necessarily recommend this particular supply at this time.
HF Power Amplifiers
HFPROJECTS.com, operated by Virgil K5OOR, offers some interesting kits which might be suitable for HPSDR project transmitting when Phoenix or Penelope becomes available, or for other transmitters. The link is http://www.hfprojects.com/newsletter.htm Two current offerings are a "pre-amp" (PA-100) for boosting a HF signal from the 100 mw range to the 5 watt or greater region, to be able to drive the SUPERPACKER PRO solid state amplifier -- a 100 watt continuous duty beast! Be aware that this is NOT an open source project, and the one submitting this information has some serious reservations about the operation of the amplifier and the project.
A Novel Grounded Base Oscillator Design for VHF/UHF Frequencies
This is a PDF file submitted by Ulrich Rohde, N1UL, which can be downloaded (about 3 MBytes) from http://hpsdr.org/downloads/GBPhaseNoiseAnalysis4-20-07.pdf
MODIFIED NORTON AMP
Submitted by Ulrich Rohde, N1UL:
This simulation using the Infineon BFP490 agrees with my test-circuit within about 0.2dB. Depending on the transformer, (2+2)/2, inductance, this works from 1 MHZ to 1 GHz max. The IP3 of about 38 dBm is excellent, the NF about 2dB. The reverse isolation can be more then 60dB, and a push-pull version has reduced IP2.
Click on the "media" link below each drawing if you want a PDF file with slightly higher resolution.