Ozy Development History

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First production board, 5 April 2007

9/22/2007: Architecture Changes

Sync detect and C&C decode now done at the output of the FX2 rather than the Rx FIFO output. This ensures we can control other cards on the Atlas bus in the event that not all clocks are fully defined. This change is necessary so that we can select the 10MHz reference clock from Gibraltar, Penelope or Mercury and also the 125MHz reference from Penelope or Mercury. Numerous code tidied up and comments updated. The Verilog diagrams have been updated to reflect the changes.

2/11/2007: Ready for production.

12/10/2006: Initial tests of Ozy V2 indicate all functions are OK - VK6APH.

11/30/2006: All Alpha 2 kits arrived (including VK6APH in Oz).

11/20/2006: All Alpha 2 kits shipped.

11/18/2006: The parts for the Alpha 2 release are in hand and kitted for the test team. The PCBs were shipped today via overnight service, and should arrive Monday, Nov 20. With luck, all Alpha 2 kits should be enroute to the testers the same day.

10/06/2006: The schematic and PCB board layout for REVB of OZY is complete. This revision corrects issues we found in OZY REVA alpha 1 boards. See OZY_REVA_ALPHA_REVLIST for issues that were corrected.

08/15/2006: All Alpha OZY boards are now working. The Janus FPGA code has been ported and is working correctly. Phil, VK6APH, had the first QSO using the OZY + Janus + Atlas combination on 12th August 2006. Check out of all the I/O functions continues.

Assembled OZY as of 14 July 2006

07/20/2006: OZY Utilities are written to allow firmware download and FPGA upload via USB using libUSB. A C# class library was written to allow the use of libUSB with C# programs and IronPython.

07/10/2006: OZY now has firmware! Work is under way to switch to libUSB instead of the Cypress driver.

07/07/2006: OZY has been completely assembled minus two components, the Dallas serial to 1-Wire converter and a diode on the logic analyzer port (parts on backorder -estimated ship date 07/07/2006). The Cypress CY7C68013A (FX2) enumerates on USB. The I2C EEPROM on board was programmed with a C0 load with VID 0xFFFE and PID 0x0007. The CyUSB.sys driver's inf file was modified to include the VID/PID. Later the LibUSB-Win32 driver will be used instead. The Cyclone II FPGA was loaded with a test program via JTAG and the test program was successfully run. The next task is to load firmware into the FX2 to allow downloading of the FPGA code over USB.

See OZY_REVA_ALPHA_REVLIST for proposed additions/changes to the OZY design before it is released for production.

See OZY_REVA_STARTUP for notes/issues on debugging/startup of the OZY alpha board.