Difference between revisions of "MAGISTER"
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''' Magister''' | ''' Magister''' | ||
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The project leader for the Magister board is Lyle Johnson, KK7P | The project leader for the Magister board is Lyle Johnson, KK7P | ||
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| + | Magister is an FPGA based interface controller card that provides a high-speed USB 2.0 interface for the Atlas bus, as well as limited additional I/O lines intended for radio control (e.g., bandswitching, CW paddle and so forth). It uses the same Altera Cyclone II FPGA as Ozy and is capable of running the current Ozy code (as of 18 September 2009). | ||
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| + | The USB interface uses a Cypress FX2 chip, supporting full duplex USB communications at > 30MB/s. | ||
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| + | The FPGA also provides the necessary control logic and data formatting for the Janus board as well serial and parallel interfaces for user defined I/O. | ||
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| + | [[Image:Magister1.gif]] | ||
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| + | Magister Development History | ||
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| + | The project was undertaken by KK7P in mid-summer 2009. Three prototypes were constructed by early September 2009. Magister loads and runs current HPSDR code. Further testing is underway as this is written (19 September 2009). | ||
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| + | Magister is initially released under NCL until TAPR has an opportunity to build an initial quantity and distribute them, after which the design materials will be re-released under OHL. | ||
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| + | Design materials will be posted soon. | ||
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| + | [[Image:Magister2.gif]] | ||
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| + | Magister prototype in operation with Mercury. | ||
Revision as of 05:51, 18 September 2009
Magister
The project leader for the Magister board is Lyle Johnson, KK7P
Magister is an FPGA based interface controller card that provides a high-speed USB 2.0 interface for the Atlas bus, as well as limited additional I/O lines intended for radio control (e.g., bandswitching, CW paddle and so forth). It uses the same Altera Cyclone II FPGA as Ozy and is capable of running the current Ozy code (as of 18 September 2009).
The USB interface uses a Cypress FX2 chip, supporting full duplex USB communications at > 30MB/s.
The FPGA also provides the necessary control logic and data formatting for the Janus board as well serial and parallel interfaces for user defined I/O.
Magister Development History
The project was undertaken by KK7P in mid-summer 2009. Three prototypes were constructed by early September 2009. Magister loads and runs current HPSDR code. Further testing is underway as this is written (19 September 2009).
Magister is initially released under NCL until TAPR has an opportunity to build an initial quantity and distribute them, after which the design materials will be re-released under OHL.
Design materials will be posted soon.
Magister prototype in operation with Mercury.
