Using Penelope with a linear amplifier
When using Penelope to drive a linear amplifier it is important to ensure that you use enough drive from PowerSDR, K.I.S.S Konsole etc. to maximize the output Signal to Noise (S/N) ratio.
The Digital to Analog Converter (DAC) used on the Penelope board is a 14 bit device. This produces a maximum theoretical S/N ratio of 84dB (though various effects reduce this in practice), which occurs when the board is being driven to its maximum output of approximately 500mW.
If the user interfaces Penelope to a linear amplifier that requires much less than this level of drive then it is advisable to place an attenuator between Penelope and the amplifier rather than reduce the drive level from the PC.
The reason for this is as follows. As the drive level from the PC is reduced, the peak power output from Penelope will be reduced in direct proportion. In effect, as drive is reduced the effective number of bits of the DAC that are being used is reduced. This will cause a degradation of the quality of the output signal due to two effects: (1) due to normal circuit effects, Penelope will always generate a small amount of unwanted output, including thermal noise, pickup of spurious signals from clock lines on the PCB, etc., (2) as dictated by sampling theory, the conversion of digital values to an analog signal will produce unwanted discrete spurious signals (spurs), whose magnitude and frequency are related to how accurate the conversion process is.
The residual noise level from Penelope is more-or-less independent of drive level, hence as the signal magnitude is reduced, this noise represents a larger fraction of the total output power, and the output S/N ratio drops.
The generation of spurs due to digital-to-analog conversion is a potentially much more significant problem. Each halving of the amplitude of the values fed to the DAC reduces the output of Penelope by about 3dB, and represents using one less bit of the DAC width. Each 1-bit reduction increases the relative magnitude of the spurs in the output, compared to the desired signal, by 6dB. Thus, as the amplitude is reduced, the signal quality goes down much faster than the signal strength does.
In an extreme case, consider if Penelope were to be used to drive a VHF transverter where only say 2mW of drive were needed. If the PC drive were to be reduced to produce this level of output from Penelope, then in effect only 6 of the available 14 DAC bits would be used.
From sampling theory, this could result in spurs of magnitude -36dBc, that is, spurs 36dB below the desired (carrier) output. This is unfortunately considerably worse than the requirements of FCC Part 97, subpart D, which requires -43dBc spurious signals for HF, and -60dBc for 6M (over 25W). To ensure that the amplified output of Penelope remains at the highest quality, and especially remains well within the allowed limits, it is best to stay as close to the full resolution of the DAC as possible, which means as close to the full output power level as possible.
Should the user wish to drive a linear amplifier that has a drive requirement of less than approximately 200mW, then an attenuator should be used between Penelope and the amplifier to enable Penelope to operate at a high power level. This will also help reduce the possibility of overdriving and even damaging the amplifier by an incorrect output level configuration setting in the PC software.
