[Xylo-SDR] Wolfson interface

["Phil Harman" <pvharman@arach.net.au>]

Hi Phil,

I find that if I simulate my interface using the 24.576MHz clock rather than 
the 12/24/48MHz  FX2 clock then it runs works OK without any Undefined 
states.

Does this mean that I need to feed this clock into the FPGA and use it 
rather than the FX2 clock?

73's  Phil..




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