Re: [Xylo-SDR] Wolfson interface

[Philip Covington <p.covington@gmail.com>]

Phil,

I am a bit confused.  What frequency is your MCLK to the Wolfson?  The
BCLK and LRCLK are synchronous with the MCLK.  If you are using some
other clock than the FX2_CLK to drive the Wolfson (which you would
have to be for 48000 sps) then the BCLK and LRCLK are asynchronous
with the FX2_CLK - which would cause problems in your state machine
(since some of its states are determined by BCLK and LRCLK).   By
using the 24.576 MHz MCLK to drive your state machine, the BCLK and
LRCLK are now synchronous with MCLK.  You would just need to feed your
MCLK into the second clk pin (CLK2, pin 66) input on the FPGA and use
that instead of the FX2_CLK.

I hope this helps... I am not quite completely awake and have not had
my coffee this morning... ;-)

73 de Phil N8VB


On 12/10/05, Phil Harman <pvharman@arach.net.au> wrote:
> Hi Phil,
>
> I find that if I simulate my interface using the 24.576MHz clock rather than
> the 12/24/48MHz  FX2 clock then it runs works OK without any Undefined
> states.
>
> Does this mean that I need to feed this clock into the FPGA and use it
> rather than the FX2 clock?
>
> 73's  Phil..
>
>
>
>
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