Re: [Xylo-SDR] Wolfson interface

["Phil Harman" <pvharman@arach.net.au>]

Phil,

Thanks for that - I was using the FX2 clock rather than the 24.576MHz clock 
in the simulation and hence the problem with undefined states. I'm not sure 
that a state machine is the best solution in this case so will revisit my 
previous solution.

Slowly up the learning curve!  Thanks for your help, much appreciated.

Phil... VK6APH


----- Original Message ----- 
From: "Philip Covington" <p.covington@gmail.com>
To: "Xylo-SDR Discussion" <xylo-sdr@lists.ae5k.us>
Sent: Saturday, December 10, 2005 10:19 PM
Subject: Re: [Xylo-SDR] Wolfson interface


> Phil,
>
> I am a bit confused.  What frequency is your MCLK to the Wolfson?  The
> BCLK and LRCLK are synchronous with the MCLK.  If you are using some
> other clock than the FX2_CLK to drive the Wolfson (which you would
> have to be for 48000 sps) then the BCLK and LRCLK are asynchronous
> with the FX2_CLK - which would cause problems in your state machine
> (since some of its states are determined by BCLK and LRCLK).   By
> using the 24.576 MHz MCLK to drive your state machine, the BCLK and
> LRCLK are now synchronous with MCLK.  You would just need to feed your
> MCLK into the second clk pin (CLK2, pin 66) input on the FPGA and use
> that instead of the FX2_CLK.
>
> I hope this helps... I am not quite completely awake and have not had
> my coffee this morning... ;-)
>
> 73 de Phil N8VB
>
>
> On 12/10/05, Phil Harman <pvharman@arach.net.au> wrote:
> > Hi Phil,
> >
> > I find that if I simulate my interface using the 24.576MHz clock rather 
> > than
> > the 12/24/48MHz  FX2 clock then it runs works OK without any Undefined
> > states.
> >
> > Does this mean that I need to feed this clock into the FPGA and use it
> > rather than the FX2 clock?
> >
> > 73's  Phil..
> >
> >
> >
> >
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Checked by AVG Free Edition.
Version: 7.1.371 / Virus Database: 267.13.13/197 - Release Date: 9/12/2005