Re: [Xylo-SDR] Your FPGA Code

["Jeff Anderson" <jca1955@sbcglobal.net>]

For what it's worth, here are a couple of notes regarding the gnd isolation
of the ckt shown in the website in the email below:

1.  The gnd isolation depends upon the "balance" of the component values in
the final stage.  Typically, it's better to avoid caps in this sort of ckt,
because, due to their larger variation in values, compared to the resistors,
they can easily unbalance an otherwise balanced ckt, and you could see the
isolation worsen at high frequencies as their impact on the circuit becomes
more and more pronounced.

2.  It looks to me that the design should have some components swapped.  For
example, in the first ckt shown, I would have connected R125 to the external
gnd (SND_GND), and the network R104, R117, and C86 to the local gnd.  (And
actually, I would have left R116/C85 and R117/C86 out of the ckt altogether,
unless there are stability issues with the op-amp).

(Regarding the swapping of components - an easy way to visualize the reason
for this is to imagine that R124, rather than being connected to IC1.6,
instead connects to the local gnd (which it effectively is connected to if
there is no input signal).  Now, drive SND_GND with a noise-source connected
between it and the local gnd.  What should the ckt configuration be to
ensure that the signal at SND1_I *exactly matches* the signal on SND_GND).
In otherwords, if the far-end gnd (where the ADC is) is bouncing up and down
with respect to the local gnd, what would you add to the outgoing local
signal so that, if you were standing at the far-end and using the far-end
gnd as reference (just as the ADC would), you wouldn't see any bouncing up
and down?

- Jeff, WA6AHL

-----Original Message-----
From: xylo-sdr-bounces@lists.ae5k.us
[mailto:xylo-sdr-bounces@lists.ae5k.us]On Behalf Of KD5NWA
Sent: Monday, December 12, 2005 4:07 AM
To: Xylo-SDR Discussion
Subject: Re: [Xylo-SDR] Your FPGA Code


Leon, are you putting the op-amp circuit in the analog input to
create a virtual ground and eliminate ground loop currents and
voltages? That is the downfall of a lot of sound cards and causes the
big hump of trash in the center of the passband. It would need to be
adapted to the input stage to subtract the PC ground level from the signal.

The last stage.

< http://www.nitehawk.com/sm5bsz/linuxdsp/rxiq/antiali.htm >


At 12:37 AM 12/12/2005, you wrote:

>----- Original Message -----
>From: "Phil Harman" <pvharman@arach.net.au>
>To: "Jeff Anderson" <jca1955@sbcglobal.net>
>Cc: "Xylo-SDR Discussion" <xylo-sdr@lists.ae5k.us>
>Sent: Monday, December 12, 2005 6:12 AM
>Subject: Re: [Xylo-SDR] Your FPGA Code
>
>
> > Jeff,
> >
> > This is simply great - I've been reading all the Verilog tutorials I can
> > find and non of your tips came up in any of them.  I am sure that many
of
> > us
> > newbies appreciate the effort that you went to in making these
> > suggestions.
> >
> > I'm making very good progress with the full implementation of the
Wolfson
> > interface and will have it ready for critique very shortly.
>
>Is that the WM8785? I was intending to use that on my Cyclone II board.
>
>Leon
>
>---
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Cecil Bayona
KD5NWA
www.qrpradio.com

"I fail to see why doing the same thing over and over and getting the
same results every time is insanity: I've almost proved it isn't;
only a few more tests now and I'm sure results will differ this time ... "

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