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Re: [Xylo-SDR] Your FPGA Code

Leon, are you putting the op-amp circuit in the analog input to create a virtual ground and eliminate ground loop currents and voltages? That is the downfall of a lot of sound cards and causes the big hump of trash in the center of the passband. It would need to be adapted to the input stage to subtract the PC ground level from the signal.

The last stage.

< http://www.nitehawk.com/sm5bsz/linuxdsp/rxiq/antiali.htm >

At 12:37 AM 12/12/2005, you wrote:

----- Original Message -----
From: "Phil Harman" <pvharman@arach.net.au>
To: "Jeff Anderson" <jca1955@sbcglobal.net>
Cc: "Xylo-SDR Discussion" <xylo-sdr@lists.ae5k.us>
Sent: Monday, December 12, 2005 6:12 AM
Subject: Re: [Xylo-SDR] Your FPGA Code

> Jeff,
> This is simply great - I've been reading all the Verilog tutorials I can
> find and non of your tips came up in any of them.  I am sure that many of
> us
> newbies appreciate the effort that you went to in making these
> suggestions.
> I'm making very good progress with the full implementation of the Wolfson
> interface and will have it ready for critique very shortly.

Is that the WM8785? I was intending to use that on my Cyclone II board.


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Cecil Bayona

"I fail to see why doing the same thing over and over and getting the same results every time is insanity: I've almost proved it isn't; only a few more tests now and I'm sure results will differ this time ... "