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Re: [Xylo-SDR] Clocks for USB FX2, TI PCM4202, etc.
Just to stir the pot...
1) Think about putting the default ADC and DAC on the main board with
the FPGA. Add connector for hooks to tie in external ones. This will
minimize RFI, of some importance if this is going inside a radio.
2) The ADC and DAC may have I2C or SPI, but that is just for control.
Typically, there is a bit clock and frame sync signals, with frame sync
in the 48 kHz to 192 kHz range and the bit clock typically 32 to 64
times faster. You can expect a 12.288 MHz bit clock in a 192 kHz sample
rate system using the PCM4202, for example. Harmonics of this can make
interesting spurs and birdies, so you might want to keep the leads
really short, which is a large part of the reason to put the ADC and DAC
on the same board with the FPGA.
3) Consider putting the ADC buffer amplifier on the same board, and make
it differential. Like the OPA1632 for the TI ADC. This could be on a
plug-in board, but then you are making a requirement to use the plug-in
if you intend to use the ADC at all.
4) For ADCs of this caliber, think differential signaling.
5) If power consumption is a consideration, consider avoiding the
Cyclone II or Spartan 3 or any of the 90 nm process FPGAs. They are
denser and cost a little less for given functionality, but the static
current drain is dramatically higher than the older, 120 nm process
parts. If power consumption is not a consideration, then go for it and
use the latest 90 nm process parts.
6) The analog section needs its own power supply regulators, well
decoupled from the digital stuff.
7) You'll likely need negative voltage at several mA for the analog
circuitry. Avoid charge pumps such as those used in RS232 converter
chips if RF noise is a concern.