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[Xylo-SDR] Update - 14th Jan 2006
A very productive week. My student finished this week and completed her
VHDL code to produce a full duplex audio interface to the PC using the
Wolfson A/D converter.
I caught up with her progress today and now have a Verilog version working.
Only 48Ks and 16 bit mono but stereo and high speed sampling rate should not
prove too difficult.
I used the example code from the fpga4fun web page to code a single bit
D/A conveter. This works very well, when clocked at ~3MHz a trivial low
pass filter produces a very nice audio output.
For testing I've written a very simple C program on the PC that talkes the
incoming USB data from the Xylo/Wolfson and sends it straight back. As
long as the PC is not doing anything else this seems to work OK. However if
you run a program such as Windows Task Manager then we regularly drop
samples. Too early to tell if this is a problem with my Verilog code or the
blocking nature of the USB drivers that Xylo provide. Perhaps one of the PC
programers could comment on this?
I want to make a few changes to my Verilog code - add stereo and a dual
clock FIFO on receive - then I'll post it on SVN.
Soon has Bill has some time he has offered to look at adding this into
PowerSDR for us to test.
73's Phil...VK6APH
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