Re: [Xylo-SDR] Xylo-SDR project details - What I want to use it for...

[Philip Covington <p.covington@gmail.com>]

On 1/17/06, vk4str <vk4str@netspace.net.au> wrote:

> When looking over the Xylo-SDR webpages and also the forum webpages I
> could not find any specific project specifications or details. Could
> someone please provide me with a link to project related information,
> thanks. Would be nice to know what is planned to go into the enclosure, hi.
>
> 73, Helmut VK4STR

This project is general enough that it could be used for even
something non-SDR related.  The FPGA-USB board and bus make it
applicable to many different projects.

I can tell you what I want to use it for:

1. I originally wanted to build a better QSD based SDR incorporating
improvements that we learned from using the SDR-1000 and SoftRock. 
After trying many different circuit "improvements" for the QSD, one
problem remains - the increasing noise figure with frequency.  So I
started to look at ADC front-ends instead of the QSD.

2. I like the GNURadio USRP,  it uses a chip that combines an ADC and
DAC into something Analog Devices calls a "mixed signal processor". 
The ADC is 12 bits, 64 MSPS and the DAC is 14 bits, 125 MSPS.  The
"flaw" with this design is that the ADC/DAC chip is on the same board
as the Cyclone FPGA and FX2 USB chip.  The FPGA does the job of
downsampling the 64 MSPS output of the ADC to a rate that can be
sustained over USB.  The FPGA implements the Digital Down Conversion
(DDC).  It also does the inverse to upsample the USB data to drive the
DAC for transmit (DUC).  To upgrade the URSP with a better ADC, the
USRP motherboard would have to be completely redesigned.  This is very
expensive.

3. The RFSpace SDR-14 is also interesting.  It uses an Analog Devices
AD6644, 14 bit, 65 MSPS ADC and the AD6620 Digital Down Converter
(DDC) chip.  The DDC performs the downsampling of the 65 MSPS to a
rate that can be handled over a USB connection.  You cannot pump 65
MSPS over USB.  The downside is that the SDR-14 uses USB 1.1 for an
interface which is too slow.  Also, it is very expensive ($1000), the
ADC cannot be upgraded in an existing unit (neither the USB to 2.0),
and it does not have TX.

4. I looked at the latest ADCs out there.  One is the Analog Devices
AD9446, 16 bit, 100MSPS ADC.  This is a big improvement over the 12
bit ADC used in the USRP and the 14 bit in the SDR-14.  It is
expensive, but it replaces many components vs. the QSD designs.  The
downside to this part is that it requires an extremely low jitter
sampling clock in squarewave form.  Even the low jitter Valpey-Fisher
part used in the SDR-1000 has enough jitter to decrease the Effective
Number of Bits (ENOB) to less than 14 bits.  In my blog, I originally
said that I intended to use the AD9446 - until I found the...

5. Linear Devices LTC2208, 16 bit, 130 MSPS ADC.  There are many
unique features of this part:  It can be fed with a sinusoidal encode
clock via a Mini-circuits 1:4 or 1:1 transformer.  There is a clock
duty cycle stabilizer on the chip.  It has a Programmable Gain
Amplifier (PGA) that lets you select two input ranges.  It has a
function that you can enable where you can randomize the digital data
out which improves dynamic range by spreading out the digital noise. 
There is a dithering function built in that can be enabled or disabled
further improving the low signal capability.

6. So, I want to build an SDR that is based on the LTC2208.  I want a
separate FPGA/USB board that could be changed out with a PCI Express
based interface in the future.  The bus structured motherboard and
DIN41612 connector plug-in cards make a good base for the project.

7. For TX, Phil - VK6APH and I have begun to discuss the possibility
of using a Class E amplifier driven by a phase signal and a magnitude
signal from the FPGA.  The phase signal would drive the Class E amp
and the magnitude signal would PWM the dc power supply to the class E
amp.  This is what the AMSAT SDX guys are doing.  It should make a
very interesting project.

73 de Phil N8VB