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Re: [Xylo-SDR] FPGA pin names in schematic

May I ask, where did you aquire the Diligent Spartan3 dev board? Googling didn't produce anything useful.
Steve - K5FR

From: xylo-sdr-bounces@lists.ae5k.us [mailto:xylo-sdr-bounces@lists.ae5k.us] On Behalf Of KD5NWA
Sent: Friday, January 20, 2006 11:32 AM
To: Xylo-SDR Discussion
Subject: Re: [Xylo-SDR] FPGA pin names in schematic

The second you use the internal PLL to multiply the clock up, your phase noise goes through the roof, making it useless as the clock for a Radio, it's OK for a computer but a Radio is way more sensitive to phase noise. That is why I have pushed for two clock modules, one for the Analog chips,  and one for who knows what, that needs low phase noise.

These parts do not have to be put in if you don't need them, but if you need them and the place for them is not there, then you have to design a whole new board, so much for being general purpose board. There are certain features that are needed on that board to make it really useful for "Radio" projects otherwise you are going to be putting in so many boards as to make the whole concept useless because of cost.

So far that board is no different that any board that is out there and you can purchase for $100 or less, so what is the point in making it? I just received a Diligent Spartan3 board for 99$, and it's loaded with resources, but it has more capability to be useful in a radio project that the strip-down model that is wanted here, Video Out, Mouse and Keyboard input, tons of high speed RAM, and multiple connectors for daughter cards, 500MHz clocking capability, multiple clock sources. It's not meant specifically meant for Ham use but it's sure handy.

That is it enough ranting, I will speak no more on this or any FPGA board subject.  Instead of talking I'll have to set some time aside to learn Eagle enough to feel comfortable with four-layer SMT boards.

At 10:26 AM 1/20/2006, you wrote:
----- Original Message -----
From: KD5NWA
To: Xylo-SDR Discussion
Sent: Friday, January 20, 2006 3:59 PM
Subject: Re: [Xylo-SDR] FPGA pin names in schematic

If we are going to have a FPGA DDS it needs to be on the FPGA board, otherwise there are too many high frequency signals flying about.

The FPGA board has headers with I/O pins? if it does, it could be a daughter board that connects directly into the FPGA board. If the FPGA card has the capability of plugging in a daughter specialty card then all sorts of projects are possible.

As far as a DAC goes, think about it, a lot of spurs are caused because the D/A does not have sufficient phase and amplitude resolution.

The FPGA has a limit around 250MHz for the clock, if you do bit diddling that is 8X at 30 MHz, that is the same as a 3 bit DAC, so what kind of spurs are you going to have? I would be totally useless, a R 2R resistor network would do way better, at least there you could get at least 8 bit's at 250MHz.

For audio,and using several MHz for the clock, your are fine, you can generate pretty good audio with a low pass or a elliptical filter.

A header for a small daughter board is the best way to go, and could be useful for other applications, so I'll add one. I'll use those tiny little Japanese connectors to save space, and keep signals as short as possible. I'd better put one or two connections to the FPGA clock inputs on it.
The FPGA doesn't need a very fast clock input, as it has clock multipliers/dividers built-in.
Pulsonix manifested a bug earlier today after my latest changes to the FPGA part - adding more nets to the pins. It always happened when I did an electrical rules check, which checks the schematic for inconsistencies, like different nets connected to the same pin. It was a serious bug and was holding me up so their software people dealt with it right away. I had a new DLL emailed to me in a couple of hours, which fixed the problem!
73, Leon
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Cecil Bayona

I fail to see why doing the same thing over and over and getting the same results every time is insanity: I've almost proved it isn't; only a few more tests now and I'm sure results will differ this time ...