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Re: [Xylo-SDR] FPGA pin names in schematic

On 1/20/06, KD5NWA <kd5nwa@cox.net> wrote:
>  The second you use the internal PLL to multiply the clock up, your phase
> noise goes through the roof, making it useless as the clock for a Radio,
> it's OK for a computer but a Radio is way more sensitive to phase noise.
> That is why I have pushed for two clock modules, one for the Analog chips,
> and one for who knows what, that needs low phase noise.

That is why I suggested having the application specific clock on the
particular plug-in board.
But, if you have two clocks on your application specific plug-in board
and they are not synchronous then you are asking for trouble in either
a DDS or ADC application... unless you are lucky.  You can get away
with it sometimes...

>  These parts do not have to be put in if you don't need them, but if you
> need them and the place for them is not there, then you have to design a
> whole new board, so much for being general purpose board. There are certain
> features that are needed on that board to make it really useful for "Radio"
> projects otherwise you are going to be putting in so many boards as to make
> the whole concept useless because of cost.

I agree.  They only problem is when you suddenly run out of space on
your single FPGA because your are trying to do DDS, GPIO, I2S, etc..
all in one project...which you could in a "radio" type project.

>  So far that board is no different that any board that is out there and you
> can purchase for $100 or less, so what is the point in making it?

Because you cannot plug those other boards into our proposed

73 de Phil N8VB