----- Original Message -----
Sent: Friday, January 20, 2006 1:29
PM
Subject: Re: [Xylo-SDR] FPGA pin names in
schematic
Phil has been looking at that, maybe he can tell us what he thinking on
the subject.
I think you need a DAC and a elliptical filter. you may
want to look at the DDS-60 board, it has all the components all figured out
for the filter and amplifier, except the DAC part
Phil Harman, or
anybody please chime in so Leon can put it in before making a
prototype.
We have been discussing how to make a cleaner DDS, and
it requires a high precision Sine table with as many as 32K to 64K entries. If
we use the internal RAM to hold those values, it being very fast, we might
need RAM on the outside for use in buffers, etc. By the way, how wide is the
RAM that you have put in? A lot of the boards that have RAM have one chip that
is 16 bits wide, so every 10 ns you can pull out a 16 bit precision number to
feed the DAC or FX2. If the internal RAM is not big enough then we are going
to need to use the external RAM and it needs to be 16 bit wide to minimize the
number of fetches.
This where a second precision optional clock device
besides the 24.4xx MHz comes in feeding a clock input pin, you want the DDS
STATE clock as high as the RAM will tolerate, if we use internal RAM for the
Sine table, our clock could be in the 200MHz range, which would give better
resolution and lower spurs.
We really need to get together on
TeamSpeak to make sure we are not leaving something critical out of the
board. >:-}
Of course all of these components are optional and
you populate the board with them if needed only.