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Re: [Xylo-SDR] FPGA pin names in schematic

If we are going to have a FPGA DDS it needs to be on the FPGA board, otherwise there are too many high frequency signals flying about.

The FPGA board has headers with I/O pins? if it does, it could be a daughter board that connects directly into the FPGA board. If the FPGA card has the capability of plugging in a daughter specialty card then all sorts of projects are possible.

As far as a DAC goes, think about it, a lot of spurs are caused because the D/A does not have sufficient phase and amplitude resolution.

The FPGA has a limit around 250MHz for the clock, if you do bit diddling that is 8X at 30 MHz, that is the same as a 3 bit DAC, so what kind of spurs are you going to have? I would be totally useless, a R 2R resistor network would do way better, at least there you could get at least 8 bit's at 250MHz.

For audio,and using several MHz for the clock, your are fine, you can generate pretty good audio with a low pass or a elliptical filter.

At 08:27 AM 1/20/2006, you wrote:
Leon,
 
I'm using a single bit over clocking D/A converter for the L/R audio so only need one pin for each.  With a high enough clock perhaps we could do the same for the  I/Q signals for the  mixer. In which case we would only need two pins and enough space for the elliptical filters and drivers.
 
Does sound like we are getting a bit too specific for what is supposed to be a GP board. On the other hand I don't have any experience of running such high frequency clocks through a DIN backplane.
 
Phil...
----- Original Message -----
From: Leon Heller
To: Xylo-SDR Discussion
Sent: Friday, January 20, 2006 10:00 PM
Subject: Re: [Xylo-SDR] FPGA pin names in schematic

----- Original Message -----
From: KD5NWA
To: Xylo-SDR Discussion
Sent: Friday, January 20, 2006 1:29 PM
Subject: Re: [Xylo-SDR] FPGA pin names in schematic

Phil has been looking at that, maybe he can tell us what he thinking on the subject.

I think you need a DAC and a elliptical filter. you may want to look at the DDS-60 board, it has all the components all figured out for the filter and amplifier, except the DAC part

Phil Harman, or anybody please chime in so Leon can put it in before making a prototype.

We have been discussing how to make a cleaner DDS, and it requires a high precision Sine table with as many as 32K to 64K entries. If we use the internal RAM to hold those values, it being very fast, we might need RAM on the outside for use in buffers, etc. By the way, how wide is the RAM that you have put in? A lot of the boards that have RAM have one chip that is 16 bits wide, so every 10 ns you can pull out a 16 bit precision number to feed the DAC or FX2. If the internal RAM is not big enough then we are going to need to use the external RAM and it needs to be 16 bit wide to minimize the number of fetches.

This where a second precision optional clock device besides the 24.4xx MHz comes in feeding a clock input pin, you want the DDS STATE clock as high as the RAM will tolerate, if we use internal RAM for the Sine table, our clock could be in the 200MHz range, which would give better resolution and lower spurs.

We really need to get together on TeamSpeak to make sure we are not leaving something critical out of the board. >:-}


Of course all of these components are optional and you populate the board with them if needed only.

I'd rather have the DAC etc. on another board. I'd like to keep the FPGA board as general-purpose as possible.
 
The RAM is 16-bits wide.
 
73, Leon
 
 

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Cecil Bayona
KD5NWA
www.qrpradio.com

I fail to see why doing the same thing over and over and getting the same results every time is insanity: I've almost proved it isn't; only a few more tests now and I'm sure results will differ this time ...