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Re: [Xylo-SDR] FPGA pin names in schematic

----- Original Message -----
From: KD5NWA
Sent: Friday, January 20, 2006 3:59 PM
Subject: Re: [Xylo-SDR] FPGA pin names in schematic

If we are going to have a FPGA DDS it needs to be on the FPGA board, otherwise there are too many high frequency signals flying about.

The FPGA board has headers with I/O pins? if it does, it could be a daughter board that connects directly into the FPGA board. If the FPGA card has the capability of plugging in a daughter specialty card then all sorts of projects are possible.

As far as a DAC goes, think about it, a lot of spurs are caused because the D/A does not have sufficient phase and amplitude resolution.

The FPGA has a limit around 250MHz for the clock, if you do bit diddling that is 8X at 30 MHz, that is the same as a 3 bit DAC, so what kind of spurs are you going to have? I would be totally useless, a R 2R resistor network would do way better, at least there you could get at least 8 bit's at 250MHz.

For audio,and using several MHz for the clock, your are fine, you can generate pretty good audio with a low pass or a elliptical filter.

A header for a small daughter board is the best way to go, and could be useful for other applications, so I'll add one. I'll use those tiny little Japanese connectors to save space, and keep signals as short as possible. I'd better put one or two connections to the FPGA clock inputs on it.
The FPGA doesn't need a very fast clock input, as it has clock multipliers/dividers built-in.
Pulsonix manifested a bug earlier today after my latest changes to the FPGA part - adding more nets to the pins. It always happened when I did an electrical rules check, which checks the schematic for inconsistencies, like different nets connected to the same pin. It was a serious bug and was holding me up so their software people dealt with it right away. I had a new DLL emailed to me in a couple of hours, which fixed the problem!
73, Leon