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Re: [Xylo-SDR] RFC - Motherboard
You are right. I ceased to panic after the first flurry on that matter.
FPGA's in the capability range we are talking about are not that expensive.
However, in this exchange which you have explained well right here:
If you used ALL the resources on the Lions 'heart' can you do what you are
planning below? Your project does NOT have to co-exist with any others, just
a different FPGA program and leverage of programs in common with other
projects like FX2. Other slots used for the BPF board etc. If so, that WOULD
make the daughter card + Buss concept viable. After all the Janus is a
totally different project, and will never need to co-exist with your radio!
It would also make the Lionheart a little more flexible in that it would
allow for a 'squatter'. I realize it depends on physical space, but
'squatting' on cleverly spaced pins could do it. Nothing has all that much
height, in any of these projects except front panel stuff.
From: email@example.com [mailto:firstname.lastname@example.org]
On Behalf Of Philip Covington
Sent: Tuesday, January 24, 2006 10:44 PM
To: Xylo-SDR Discussion
Subject: Re: [Xylo-SDR] RFC - Motherboard
On 1/24/06, Eric Ellison <email@example.com> wrote:
> Apologies, I was not intending to offend, just to question the buss
> I previously agreed with you on your suggestion of a separate FPGA. It IS
> the right way to go with the radio. (Need to name it something, smile)
> Guess we are all tired of the circles. Let's move on.
> It does not seem that the Janus or other probable offshoot boards will
> additional FPGA's.
> Are there enough resources, space and to put it on the Lionheart? Both you
> and Cecil are talking about doing the same thing with the same chip. Also
> that pretty much means you are only needing the FX2 on Lionheart. I may
> missed something in that discussion.
I am not offended, so no problem. I just don't understand why people
panic when I mention more than one FPGA... LOL... I don't think of
them any differently than any other chip - if I need two then I use
Here is the deal with the LTC2208: We can't shove 130 MSPS down USB
and if we could I doubt the PC would keep up anyhow. What we do is
downsample the 130 MSPS in the FPGA to, let's say, 512 kSPS 16 bit I/Q
data. We use a NCO in the FPGA to put the signals we are interested
somewhere in that 512 kHz bandwidth. What we have coming out of the
FPGA at this point is 512 kSPS 16 bit I/Q, just like we have 192 kSPS
24 bit I/Q data coming out of the Wolfson/TI chip. Now since the
Lionheart FPGA board can handle the 192 kSPS 24 bit I/Q data from Phil
H's Janus board, it won't be pushing it much to handle the 512 kSPS 16
bit I/Q data from the LTC2208 board. Once it is into the Lionheart we
can process the data from that point on the exact same way we process
the data from Phil H's Janus board.
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