[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Xylo-SDR] RFC - Motherboard
On 1/24/06, Eric Ellison <email@example.com> wrote:
> Apologies, I was not intending to offend, just to question the buss concept.
> I previously agreed with you on your suggestion of a separate FPGA. It IS
> the right way to go with the radio. (Need to name it something, smile)
> Guess we are all tired of the circles. Let's move on.
> It does not seem that the Janus or other probable offshoot boards will need
> additional FPGA's.
> Are there enough resources, space and to put it on the Lionheart? Both you
> and Cecil are talking about doing the same thing with the same chip. Also
> that pretty much means you are only needing the FX2 on Lionheart. I may have
> missed something in that discussion.
I am not offended, so no problem. I just don't understand why people
panic when I mention more than one FPGA... LOL... I don't think of
them any differently than any other chip - if I need two then I use
Here is the deal with the LTC2208: We can't shove 130 MSPS down USB
and if we could I doubt the PC would keep up anyhow. What we do is
downsample the 130 MSPS in the FPGA to, let's say, 512 kSPS 16 bit I/Q
data. We use a NCO in the FPGA to put the signals we are interested
somewhere in that 512 kHz bandwidth. What we have coming out of the
FPGA at this point is 512 kSPS 16 bit I/Q, just like we have 192 kSPS
24 bit I/Q data coming out of the Wolfson/TI chip. Now since the
Lionheart FPGA board can handle the 192 kSPS 24 bit I/Q data from Phil
H's Janus board, it won't be pushing it much to handle the 512 kSPS 16
bit I/Q data from the LTC2208 board. Once it is into the Lionheart we
can process the data from that point on the exact same way we process
the data from Phil H's Janus board.