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Re: [Xylo-SDR] RFC - Motherboard

Now you know why I am so frustrated with the insistence by many that the FPGA board be nothing but FPGA card.

The traffic from some of the proposed devises is massive, or have very high frequency clocks, some of that stuff needs to be on the FPGA card, at least on a daughter card that can connect without wires all over the place. Phil's approach to use a high speed DAC to take the place of the QSD will have hundred's of megabytes per second traffic unless you use sub-sampling and that has it's own set of problems, it needs a direct connection to a high speed FPGA do process that volume of data and turn it into a reasonable stream that can then go on the USB connection. People keep taking about a digital oscilloscope, it has the same problem, massive amounts of data. You could design the bus for really high speed, but that will cost money. 4 layers minimum, active termination, it's way cheaper to have a high speed A/D connect directly on the FPGA card.

The D/A using the Wolfson or whatever can be on a daughter card that plugs into the FPGA or it's own card on the bus, but it's clock might need to go the LVDS route, that clock is not too high, so it could go on the bus if we use a 4-layer board and termination. Phil's nuclear A/D needs to connect to  the FPGA with 16 bit parallel data connections so it can get the data in at all. If you are going to measure the 200Mhz clock you need to bring that straight into the FPGA card otherwise you are looking at more expense and trouble.

Nothing wrong with the bus, most signals to many accessories will be fine on it, but there is just enough high speed stuff that we better think about using an alternative way, the easiest way, is to have several daughter connectors on the FPGA to plug in at least two boards, and one of them needs to have 16 bits for just the data + extra signals for control.

I know that the Xilinx FPGA's have for a fact LVDS drivers and receivers, I believe the Altera also does, I will check tomorrow to make sure.


At 08:10 PM 1/24/2006, you wrote:

Folks
 
Well now we are at the point of our Saturday discussion. How fast? How Clean, How Many? None of us knew, and we still don?t. Cecil did know and all of you have pointed to the solution - lvds. The buss stuff really all started to unravel when Phil_C said he needed an FPGA on the Radio board due to the probable lack of capability of the buss to carry the A/D and other high speed sigs to and from the Lionheart. Bill ? KD5TFD and I sort of said the same thing Saturday:  ?If we can?t leverage the Lionheart for all buss mounted FPGA projects now and in the future, what is the point of the buss?? It would be nice to see any pin pair be able to pass any frequency quietly. If it?s not possible then it?s not possible. Also according to Cecil, an FPGA interfaced to an FPGA can do lvds without any additional components but we still need twisted pair, or coax.
 
Cecil suggested a .100 pin header  to which we would attach a twisted pair to a single pair block going from board to board. It is a good idea for a couple of pairs of pins, but if we need 16 pair or probably more, it is a little impractical, but do-able.
 
I made a couple of suggestions for mass termination or even a ?flexible buss? using twisted pair IDC cable which didn?t garner any comments. This stuff does have flats and twists so also may be impractical.
 
Call the ball!
 
Eric
 
 
 
 
 
 
 
From: xylo-sdr-bounces@lists.ae5k.us [ mailto:xylo-sdr-bounces@lists.ae5k.us] On Behalf Of KD5NWA
Sent: Tuesday, January 24, 2006 7:34 PM
To: Xylo-SDR Discussion
Subject: Re: [Xylo-SDR] RFC - Motherboard
 
I've built Computer systems using 2X EuroCards using double connectors and no problems whatsoever back in early 80's, at that time the clock speed was 50MHz. Even though it was a two layer motherboard the signals were absolutely clean with no ringing and coupling between lines, part of that was because of massive ground planes where possible and the signals were isolated in groups with common timing with three ground pins between groups. The system clock was isolated all by itself away from other signals. Power was on the outsides of the connectors with massive pours of copper to keep the power bus impedance low. It was not a radio however.

That being said if you have 50MHz to 1000MHz signals, LVDS will keep those signals very clean if you use tightly twisted wires such as the ones found inside a CAT5e cable. I would assume that there would not be too many such signals that have to move from card to card.

My suggestion is as before if you have a very high frequency signal that you want to distribute between cards, do it on a connector on the top of the card, using LVDS signalling and twisted cables, or use coaxial cables with SMT connectors, but be aware that the output of a FPGA or logic is not too happy with coaxial cables due to impedance mismatch, which causes ringing and phase jitter, you know it as high SWR and it's reflections. LVDS is meant to use tightly twisted wires with 110 Ohm impedance and a terminating resistor, which is exactly what CAT5e cabling is, you add the resistor on the receiver side if it does not have one built in.

The original box was fine with me, all we needed was an additional 1/8" between the cards and the front plate, which I feel board mounted connectors could tolerate. But if you are going to use a tiny MicroATX PC case, that is fine too since there are many choices on the cabinet, I pointed one yesterday that was reasonable in size and very inexpensive ($27). The one I pointed out allowed easy access to the boards and had plenty of room for other components such as ovens or GPS satellite receivers.

If we allow for three pairs of signals that can be programmed as a LVDS driver to a Berg header on the top of the FPGA card, that will allow us if needed to pipe a high speed clock out of or into the FPGA in case the bus has problems with noise radiation.


At 05:38 PM 1/24/2006, you wrote:

Folks
 
Or should I say Motherboard Woes.
 
Cecil, Bill, Steve and I had a pretty long Teamspeak session last Saturday discussing buss speed. What speeds CAN we put on our buss?
None of us really knew! Cecil knew a lot about LVDS and twisted pair, but we dont have a twisted pair or coax buss! In fact we tried to figure a way to get it into our tiny, cramped, custom designed enclosure, which prompted my departure from the enclosure, buss connectors, etc.
 
However, the question remains! How DO we design our buss to go the 133 mhz PCI standard or increasing speeds in the later PCI standards. (800 mhz and beyond?) Can we even go 24 mhz to the FPGA, divide by 2 and send it back to the Janus?
 
My thought was to try to copythe PCI standards (Not the connector, just the board spec for the standard). I found again, as I knew before, PCI standards group is a private industry culb with a high price to join. When you get right down to finding out more than the buss labels, there aint much but general info. If you take a look at a mother board or even a riser you sure cant see the innards! There aint no schematics ANYWHERE I can find!
 
I did find some info in a pdf from a PCI Bridge Chip manufacturer, on how to design with their chip which yielded some light on the board design for 133 mhz.
 
I didnt have time to read all the stuff and it was a bit beyond me, however I did see one highlight as to how the PCI buss needs to be in order to support high speed design.
 
The clocks and other Critical signalsgo on the top surface of the board.
This is followed by a groundplane layer.
Followed by the Power supplies layer
Followed by the bottom Signallayer (which I took to mean slow speed stuff).
 
 
 
That was pretty sketchybut it was the description and perhaps a start. Is this doable for our MB?
 
I would hate to design and produce a motherboard which couldnt even pass I2C stuff without causing noise everywhere else. This needs to be versatile and QUIET.
 
Any suggestions as to where to go with a quiet, high speed MB design?
 
Thanks
Eric
 
 
 
 
 
 
 
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Cecil Bayona
KD5NWA
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I fail to see why doing the same thing over and over and getting the same results every time is insanity: I've almost proved it isn't; only a few more tests now and I'm sure results will differ this time ...
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Cecil Bayona
KD5NWA
www.qrpradio.com

"I fail to see why doing the same thing over and over and getting the same results every time is insanity: I've almost proved it isn't; only a few more tests now and I'm sure results will differ this time ... " 


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