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Re: [Xylo-SDR] RFC - Motherboard

Leon Heller, G1HSM
----- Original Message ----- From: KD5NWA
To: Xylo-SDR Discussion
Sent: Wednesday, January 25, 2006 7:19 AM
Subject: Re: [Xylo-SDR] RFC - Motherboard

Now you know why I am so frustrated with the insistence by many that the FPGA board be nothing but FPGA card.

The traffic from some of the proposed devises is massive, or have very high frequency clocks, some of that stuff needs to be on the FPGA card, at least on a daughter card that can connect without wires all over the place. Phil's approach to use a high speed DAC to take the place of the QSD will have hundred's of megabytes per second traffic unless you use sub-sampling and that has it's own set of problems, it needs a direct connection to a high speed FPGA do process that volume of data and turn it into a reasonable stream that can then go on the USB connection. People keep taking about a digital oscilloscope, it has the same problem, massive amounts of data. You could design the bus for really high speed, but that will cost money. 4 layers minimum, active termination, it's way cheaper to have a high speed A/D connect directly on the FPGA card.

The D/A using the Wolfson or whatever can be on a daughter card that plugs into the FPGA or it's own card on the bus, but it's clock might need to go the LVDS route, that clock is not too high, so it could go on the bus if we use a 4-layer board and termination. Phil's nuclear A/D needs to connect to the FPGA with 16 bit parallel data connections so it can get the data in at all. If you are going to measure the 200Mhz clock you need to bring that straight into the FPGA card otherwise you are looking at more expense and trouble.

Nothing wrong with the bus, most signals to many accessories will be fine on it, but there is just enough high speed stuff that we better think about using an alternative way, the easiest way, is to have several daughter connectors on the FPGA to plug in at least two boards, and one of them needs to have 16 bits for just the data + extra signals for control.

I know that the Xilinx FPGA's have for a fact LVDS drivers and receivers, I believe the Altera also does, I will check tomorrow to make sure.

From the Cylcone II data:

"Each Cyclone II device I/O pin is fed by an IOE located at the ends of LAB
rows and columns around the periphery of the device. I/O pins support
various single-ended and differential I/O standards, such as the 66- and
33-MHz, 64- and 32-bit PCI standard, PCI-X, and the LVDS I/O standard
at a maximum data rate of 805 megabits per second (Mbps) for inputs and
640 Mbps for outputs."

73, Leon