To: "Xylo-SDR Discussion" <xylo-sdr@lists.ae5k.us> Sent: Friday, January 27, 2006 3:24 AM Subject: Re: [Xylo-SDR] Lionheart Block diagram v1.2
I think there is a logistical problem with feeding the FX2 clock from the 48MHz clock/2 from the FPGA. Until the FPGA is programmed we don't get the24MHz clock for the FX2 and we can't program the FPGA via the USB until the USB is running. Whilst we could use the JTAG I suspect that most users willwant to use the USB to program. Seems we need to do like the Xylo - use a 24MHz crystal on the FX2 and feed 48MHz from the FX2 to the FPGA.
Yes, that is a problem. Might as well do that.Leon