Re: [Xylo-SDR] Lionheart Block diagram v1.2

[pvharman@arach.net.au]

I think there is a logistical problem with feeding the FX2 clock from the 
48MHz clock/2 from the FPGA. Until the FPGA is programmed we don't get the 
24MHz clock for the FX2 and we can't program the FPGA via the USB until the 
USB is running.  Whilst we could use the JTAG I suspect that most users will 
want to use the USB to program. Seems we need to do like the Xylo - use a 
24MHz crystal on the FX2 and feed 48MHz from the FX2 to the FPGA. 

Phil...VK6APH 
 
 





Quoting Leon Heller <leon.heller@bulldoghome.com>:

> ----- Original Message ----- 
> From: <pvharman@arach.net.au>
> To: <vk4str@netspace.net.au>; "Xylo-SDR Discussion" <xylo-sdr@lists.ae5k.us>
> Sent: Friday, January 27, 2006 1:41 AM
> Subject: Re: [Xylo-SDR] Lionheart Block diagram v1.2
> 
> 
> > Hi Helmut,
> >
> > Adding serial ports to the FPGA is very easy, I already have one on my 
> > Xylo to
> > help with debugging.
> >
> > Based on current feedback I will make the following changes to the V1.2
> > Lionheart block diagram
> >
> > 1. 1.2v regulator to run off the 5v rail.
> > 2. Use I2C for controlling the LPF's and BPF's. Last night I tested an
> > MCP23016 16 bit I/O expander on my Xylo and it works just fine.
> > 3. I think that I understand how the JTAG boundary scan works now so I 
> > will
> > change the diagram to show the connector going into the FPGA and from the 
> > FPGA
> > out over the bus.
> >
> > In regards to the question below, what version of the FX2 are we planning 
> > i.e.
> > how many pins?
> 
> I was intending to use the 56 pin version.
> 
> Leon 
> 
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