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[Xylo-SDR] Lionheart Block diagram v1.3
Lionheart V1.3 uploaded at
and GIF version at
- 1.2v regulator runs of +5v rail
- JTAG goes into FPGA and out to bus
- FPGA clock comes from 24MHz x 2 from FX2
- removed 20 pins for BPF and LPF, will use I2C I/O chip on filter board
- added MAX232 for RS232 comms port.
Still lots of unanswered questions:
1. Do we put USB socket on board or use common PC MB header and plug/socket
2. What plugs/sockets for 1pps/DDS clock/Control/RS232? I suggest SMB for
1pps and DDS clock.
3. What goes to the DIN connector marked ?????
4. Are we just going to use the FX2 in its "enumerate and get out of the way
mode" or in GPIF mode? If the latter should we add an EPROM to it just as
allowed for on the Xylo?