[Xylo-SDR] Staus update and HELP WANTED!

["Phil Harman" <pvharman@arach.net.au>]

Fellow Xylons,

Most will know by now  that Bob and I had a very constructive last few 
weeks.  Bob has added support for the Xylo/Wolfson A/D  and D/A into 
PowerSDR at 48k/16 bit and intial test are very incouraging.
We recently changed the sync sequence from once in evey  2 L/R samples to 
once at the start of 512 bytes. This  reduces the sync overhead and allows 
us to add command and control signals (C&C) within the audio data.
Bill has tested the new sync format within PowerSDR and again all looks 
good. I have also tested a simple C&C in that pressing the button on the 
Xylo turns the red LED off.  This simulates a PTT.
I've also added  48k/24bit  and 96k/24bit   A/D for the Wolfson and Bill is 
going to test this shorltly.
Next I'm going to breadboard the  TLV320AIC23B as a mic/line in device A/D 
and headphone/line out  D/A device.
This chip makes extensive use of I2C to initially set up various parameters 
and then adjust levels and gains etc. We need to be able to do this from the 
FPGA and therefor need an I2C Master developed in Verilog.
There  is a potential source of such code at  www.opencores.com  but it will 
need porting and testing on the Xylo.  The opencores documentation looks 
very good and the task not too onnerouse.  We really could do with some help 
if were are to move this project on at a good rate of progress.  So if 
someone would like to tackle the I2C master then it would be a nice little 
self contained project.
We also need a PCB designer to layout the  Janus board. Whilst Bill and I 
will get round to it eventually I prefer breadboards and Bill's programing 
skills, in my veiw, are much more valuable working on code at the moment. 
This does not mean we will not eventually produce a PCB - it will just take 
significantly longer (and if left up to me much longer!).
Anyone interested in helping please step up!

73's  Phil...VK6APH



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