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Re: [Xylo-SDR] LVDS buss topologies

>> If you treat is as a transmission line with proper impedance of the
>> line and termination and you will be OK. Keep the stubs short.
>> Designing the proper impedance using trances in a PCB is hairy,
>> because different manufactures use boards with different dielectric
>> constants making it tough to keep the SWR constant, unless you limit
>> yourself to a particular board.
>The variation in DC won't make much difference, variations in track width in 
>the etching process will probably have a greater effect. FR4 is generally 
>used for this sort of application in much more critical systems than ours. 
>The calculations are quite straightforward, anyway, so we could check my 
>assumption by taking a few manufacturers figures for their material.and 
>calculating the effect.
>73, Leon 
The Er of generic FR4 spans quite a range. I’ve seen it range from around 4.1 up to almost 5. The Er is bounded by the Er of glass on one end and the Er of epoxy on the other. Depending on the exact ratio of glass to epoxy the material vendor uses the Er varies.
Board fab vendors generally use material from known sources and know the materials characteristics. Therefore, if you are dealing with a specific fab house you’ll probably find the biggest driver of impedance variation is variations in etch width as pointed out by Leon since the Er is probably going to stay constant.
To check Leon’s assumption about the trace width variation causing more effect than the Er, here are some numbers to consider.
Stripline Topology
38.5 mils between planes
Nominal width 15 mils +/- 1 mil
Er 4.1 to 4.7
Width = 15
Er = 4.1 => Z = 52.27 ohms
Er = 4.7 => Z = 48.8 ohms
Now hold the Er constant at 4.1
Width = 14 mils => Z = 53.99 ohms
Width = 16 mils => Z = 50.67 ohms
In this particular case the impedance variation is about the same +/- for either Er variation of trace width variation.
For commercial boards where you can justify the cost, people quite often specify the critical nets as impedance controlled at a specific impedance and leave it up to the fab vendor to tweak their process (i.e. adjust etch width, substrate thickness etc…) to achieve the desired impedance called out in the fab drawing. This assures you’ll get your requested impedance, but the actual trace widths may deviate +/- from what you may have initially calculated. This come$ at a price.
All that being said, I’m leaning towards keeping the critical LVDS traces off of the ATLAS board.
-Ray   WB6TPU