Re: [Xylo-SDR] Pin assignment error on Xylo/Wolfson prototype schematic

["Phil Harman" <pvharman@arach.net.au>]

The pin assignments I posted in the Janus schematic are different to what 
Bill and I are using at then moment. I made these changes so that a simple 
ribbon cable can be used to connect the Janus board to the Xylo/Saxo.  When 
we get to the PCB stage we will update the Verilog code accordingly.

73's  Phil...VK6APH


----- Original Message ----- 
From: "Bill Tracey" <bill@ewjt.com>
To: "Xylo-SDR Discussion" <xylo-sdr@lists.ae5k.us>
Sent: Sunday, February 26, 2006 1:49 AM
Subject: [Xylo-SDR] Pin assignment error on Xylo/Wolfson prototype schematic


> For folks building up a Xylo/Wolfson prototype based on the schematics I
> posted - just discovered an error on the posted schematic.  The posted
> schematic shows FPGA pin 70 tied to FPGA pin 66.  In fact, it should show
> FPGA pin 69 tied to FPGA pin 66, and FPGA pin 70 should be a no
> connection.   This is based on the pin assignments the verilog code Phil
> and I have been passing around.
>
> I will probably post an updated schematic with the correction and the
> TLV320AIC23B  setup at the end of the weekend (once I get it wired and
> tested).
>
> Regards,
>
> Bill (kd5tfd)
>
>
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