[Xylo-SDR] Pin assignment error on Xylo/Wolfson prototype schematic

[Bill Tracey <bill@ewjt.com>]

For folks building up a Xylo/Wolfson prototype based on the schematics I 
posted - just discovered an error on the posted schematic.  The posted 
schematic shows FPGA pin 70 tied to FPGA pin 66.  In fact, it should show 
FPGA pin 69 tied to FPGA pin 66, and FPGA pin 70 should be a no 
connection.   This is based on the pin assignments the verilog code Phil 
and I have been passing around.

I will probably post an updated schematic with the correction and the 
TLV320AIC23B  setup at the end of the weekend (once I get it wired and 
tested).

Regards,

Bill (kd5tfd)