Difference between revisions of "Verilog"
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| [http://verilog.openhpsdr.org/Lecture_06_1280by960_MP4.rar 43 MB] | | [http://verilog.openhpsdr.org/Lecture_06_1280by960_MP4.rar 43 MB] | ||
| [http://verilog.openhpsdr.org/Lab6.rar Labs] | | [http://verilog.openhpsdr.org/Lab6.rar Labs] | ||
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| + | | Lecture 7: Compiler Directives, Parameters, Files, Testbenches, Abstracting Operations. Bus Functional Models and Simulations | ||
| + | | [http://verilog.openhpsdr.org/VerilogLecture07_20080223.rar 32MB] | ||
| + | | | ||
| + | | [http://verilog.openhpsdr.org/Lab7.rar Labs] | ||
| + | |- | ||
| + | | Lecture 8: CPU Bus Functional Models. State Machines and code walk through of the "One-Wire" protocol. Bus Functional Models, Adding Observability, Full simulation and Timing Delays. | ||
| + | | [http://verilog.openhpsdr.org/Lecture_08_1280by960_WMV.rar 132MB] | ||
| + | | [http://verilog.openhpsdr.org/Lecture_08_1280by960_MP4.rar 116MB] | ||
| + | | [http://verilog.openhpsdr.org/Lab8.rar Labs] | ||
| + | |- | ||
| + | | Lecture 9: Synthesis Technology. Code walk through and simulation of the "N-Wire" Protocol. The Synthesis Process, Abstraction Levels, Register Transfer Language (RTL), Guidelines, Operators, Statements, Indexes, Inference, Resetting, Synchronous and Asynchronous Circuits. | ||
| + | | [http://verilog.openhpsdr.org/lecture_09_1280by960_WMV.rar 146MB] | ||
| + | | [http://verilog.openhpsdr.org/Lecture_09_1280by960_MP4.rar 105MB] | ||
| + | | [http://verilog.openhpsdr.org/Lab9.rar Labs] | ||
| + | |- | ||
| + | | Lecture 10: Synthesis Continued. Fan-In Logic, State Machines, Clocks and Timing considerations, Clock domains and Crossing Clock Domains. "N-Wire" as an example of dealing with issues crossing clock domains | ||
| + | | [http://verilog.openhpsdr.org/Lecture_10_1280by960_WMV.rar 101MB] | ||
| + | | [http://verilog.openhpsdr.org/Lecture_10_1280by960_MP4.rar 75MB] | ||
| + | | [http://verilog.openhpsdr.org/Lab10.rar Labs] | ||
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The complete list of lectures is available at [http://verilog.openhpsdr.org/ http://verilog.openhpsdr.org/]. | The complete list of lectures is available at [http://verilog.openhpsdr.org/ http://verilog.openhpsdr.org/]. | ||
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| + | [[Category:Developer resources]] | ||
Latest revision as of 11:03, 25 January 2010
Verilog is a hardware description language used to model processes in the FPGAs of several HPSDR boards.
A course was presented by Kirk Weedman. It consisted of ten one hour recorded lectures on how to program in Verilog, including tools usage, and another five lectures on code walk-throughs for the code inside of Mercury, Penelope, Ozy, and the signal flows between them. Many lectures have an additional half hour of demonstrations or examples of the programming and simulation tools in the context of the lecture's topics.
Lectures 1 through 10 are about learning to program in Verilog.
Lectures 11 through 16 are special topics, focusing on the Verilog code as used inside of Mercury, Ozy, and Penelope, issues, and improvements being developed by Kirk for communicating between the modules, which all are in separate clock domains.
| Lecture Title | WMV format | MP4 format | Lecture notes and Labs |
|---|---|---|---|
| Lecture 1: Verilog as a Hardware Description Language (HDL) Overview, Introduction, Syntax and Rules. | * | * | * |
| Lecture 2: The Verilog Hardware Description Language. Registers, Assignments, Operators, Statements, Functions, Tasks. | 28MB | 64MB. Sometimes blocked by chat window, hopefully it's OK. | 53MB iPhone video, Labs |
| Lecture 3: What Good is Verilog? Programming Structure, Concurrent Processes, and The Notion of Time, Blocking Assignments, and The Simulation Process. | 65MB | Labs | |
| Lecture 4: Non-Blocking Assignments, and much more on Simulation Process | 123MB | 85MB | Labs |
| Lecture 5: Digging Deeper, Strengths, Decompositions, I/O Assignments, Time and Time Scales Parameters and Primitives | 90MB | 65MB | Labs |
| Lecture 6: Input/Output, Formatting, Monitoring, Files, "disable, fork and join" Statements Proceedural Continuous Assignments. Dealing with Delays | 64MB | 43 MB | Labs |
| Lecture 7: Compiler Directives, Parameters, Files, Testbenches, Abstracting Operations. Bus Functional Models and Simulations | 32MB | Labs | |
| Lecture 8: CPU Bus Functional Models. State Machines and code walk through of the "One-Wire" protocol. Bus Functional Models, Adding Observability, Full simulation and Timing Delays. | 132MB | 116MB | Labs |
| Lecture 9: Synthesis Technology. Code walk through and simulation of the "N-Wire" Protocol. The Synthesis Process, Abstraction Levels, Register Transfer Language (RTL), Guidelines, Operators, Statements, Indexes, Inference, Resetting, Synchronous and Asynchronous Circuits. | 146MB | 105MB | Labs |
| Lecture 10: Synthesis Continued. Fan-In Logic, State Machines, Clocks and Timing considerations, Clock domains and Crossing Clock Domains. "N-Wire" as an example of dealing with issues crossing clock domains | 101MB | 75MB | Labs |
The complete list of lectures is available at http://verilog.openhpsdr.org/.
