Difference between revisions of "PENELOPE"

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==PENELOPE - Companion Exciter to Mercury==
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'''PENELOPE - Companion Exciter to Mercury'''
  
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28th March 2007 - Update.
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[[Image:DUC-v11.jpg|thumb|400px|block diagram of the Penelope DUC]]
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<nowiki>
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The '''Penelope''' digital up converter (DUC) is a 1/2-watt transmitter/exciter board. It makes a good companion to the [[MERCURY|Mercury]] HF direct sampling receiver board. When connected to the [[ATLAS|Atlas]] (bus) it will  process the I and Q signal from the personal computer.
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  Block diagram updated to reflect prototype PCB layout.
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  Updated Alpha schematic (XA13) for Penelope is here : http://www.hamsdr.com/personaldirectory.aspx?id=534
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  Initial PCB Layout posted here: http://www.hamsdr.com/personaldirectory.aspx?id=535
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  Initial BOM posted here: http://www.hamsdr.com/personaldirectory.aspx?id=536
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</nowiki>
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17th February 2007 - Update. Block diagram updated to reflect latest schematic.
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14th February 2007: Preliminary Alpha schematic (XA8) for Penelope is here : (replaced 28 Mar 2007)
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The project leader for the board was Phil VK6APH with KK7P doing the PCB layout.
  
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8th February 2007 - Update. Block diagram updated to reflect current Breadboard design.
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''NOTE: Penelope is being manufactured by Gerd, DJ8AY. It has also been superseded by [[Pennylane]] which is available from [http://www.iquadlabs.com iQuadLabs]
  
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7th February 2007 - Update. Block diagram updated to reflect design feedback. Breadboard built, tested and working. Prototype PCB layout started.
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[[Image:penny-5.png|thumb|300px|Wide band spurious output by John N8UR. Penelope producing 0.25w out on 14.1MHz]]
  
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3rd February 2007 - Initial Specification
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[[Image:penny-spectrumplot.png|thumb|300px|Phase noise plot by John N8UR. Penelope producing 0.25w out on 14.1MHz and phase locked to on board 10MHz TCXO]]
  
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The Atlas compatible transmitter will use Digital Up Conversion (DUC) techniques and process the I and Q signal from the PC (or Sasquatch DSP board) directly without the need for a sound card.
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[[Image:Penelope_Verilog.jpg|thumb|400px|Verilog block diagram]]
  
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Some of the planned features include:
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== See Also ==
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* [[Penelope - Development History‎]]
  
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  1.8 - 55MHz frequency coverage
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* [[Penelope - Manufacturing]]
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  0.5W pep output
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  Low level transverter output
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  AM, C-AM, FM, CW, PSK etc
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  RF phase and magnitude outputs for future Envelope Elimination and Restoration (EER) power amplifier
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  Open drain FET for PTT control of external amplifiers
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  Seven open collector outputs for Linear, relay etc control,
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  Solid state antenna changeover relay for fast QSK.
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  Optional on board microphone ADC or use with a Janus card
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  Frequency options: 
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  o On board high performance 125MHz crystal oscillator
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  o External 125MHz source
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  o On board oscillator can be phase locked to 10MHz reference e.g. Gibraltar
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  o On board 10MHz OCXO/TCXO  option
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  FPGA based DUC enabling future code upgrades
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  USB interface to PC via Ozy board
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  I and Q balanced adjustment not required due to digital generation of RF waveform
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  ADC for ALC or PA linearization etc.
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  ALC processed in the FPGA to avoid  delays associated with PC processing 
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* [[Penelope - Trouble_Shooting]]
  
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Lyle, KK7P, has kindly agreed to lay out the PCB. Please provide feedback, comments and feature requests via the hpsdr reflector.
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* [[Never Short a Penelope by AD9DP|Never Short a Penelope]]
  
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Phil... VK6APH
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[[Category:Penelope| ]]
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A block diagram is shown below.
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[[Image:DUC-v9.jpg]]
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Latest revision as of 11:49, 15 September 2011

PENELOPE - Companion Exciter to Mercury

block diagram of the Penelope DUC

The Penelope digital up converter (DUC) is a 1/2-watt transmitter/exciter board. It makes a good companion to the Mercury HF direct sampling receiver board. When connected to the Atlas (bus) it will process the I and Q signal from the personal computer.

The project leader for the board was Phil VK6APH with KK7P doing the PCB layout.

NOTE: Penelope is being manufactured by Gerd, DJ8AY. It has also been superseded by Pennylane which is available from iQuadLabs

Wide band spurious output by John N8UR. Penelope producing 0.25w out on 14.1MHz
Phase noise plot by John N8UR. Penelope producing 0.25w out on 14.1MHz and phase locked to on board 10MHz TCXO
Verilog block diagram

See Also

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