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Re: [Xylo-SDR] FPGA board

Be careful the clock pins are not swapable with ordinary i/o pins, the FX2 clock and the module clock need to be connected to clock inputs. 

At 06:19 AM 1/17/2006, you wrote:

----- Original Message -----
From: "Phil Harman" <pvharman@arach.net.au>
To: "Xylo-SDR Discussion" <xylo-sdr@lists.ae5k.us>
Sent: Tuesday, January 17, 2006 11:54 AM
Subject: Re: [Xylo-SDR] FPGA board


> Leon,
>
> If I leave the RESERVED pin on the FX2 on the Xylo open (normally
> connected
> to 0v) then the FX2 can not be detected as a USB device by the PC. I
> suggest
> that you put a pad by this bin and a earth nearby just in case we need to
> jumper it.

I've actually added a header for a jumper.

>
> Also the Xylo lets you select 12/24/48MHz  from the FX2 as a clock input
> to
> the Cyclone .  It's important that the FX2 clock is available on an FPGA
> pin
> since all the USB reads/writes have to be sync to this clock.

I've added the connection from CLKOUT to the FPGA.

Latest version has been uploaded.

The Pulsonix software I use allows me to assign a pin swap condition to any
pin. I've done that for the FPGA so that connections may be optimised on the
PCB, and the schematic back-annotated with any changes.

73, Leon

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