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Re: [Xylo-SDR] Lionheart Block diagram v1.3
Good feedback - thanks.
Quoting Lyle Johnson <firstname.lastname@example.org>:
> Looks good, Phil!
> A couple observations:
> 1) Is the FX2 +3V3 source from the LM1086 or the backplane +3V3? The
> two parts should get power form the same supply, I think.
I suggest the LM1086 but perhaps Leon can confirm.
> 2) We might want to consider a "master reset" (nRESET, low means reset
> is asserted) signal derived from the +5 and +3.3V supplies (or just the
> +5 if we are making our local voltages on Lionheart from it) so we
> don't have a situation where multiple processors (including soft ones in
> various FPGAs) don't have a complex synchronization regime, and also to
> prevent a device (FPGA?) from asserting its output pins while the remote
> device(s) are still waiting for power. Nasty things can happen.
> If the reset is done with open-drain/collector, then all the boards can
> "vote" and no one comes out of reset until the decision is unanimous.
> It also allows a watchdog on one board to optionally reset the entire
> I suggest the pull up to the nRESET signal be tied to +3V3 (which +3V3?).
How about a MAX6454 uP supervisor device connected to the +5v rail from the PC