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Re: [Xylo-SDR] Fundamental Atlas design decisions
On 2/22/06, Lyle Johnson <firstname.lastname@example.org> wrote:
> > Question:
> > If the DSP board proposed by Lyle were to be used is it
> > envisioned that it would be sitting on the LVDS buss? If so would
> > it be listen only or would it drive the buss at times ??
> Depends entirely on what the I/O requirements are for the other boards.
> The DSP board needs to communicate with the audio I/O and "IF I/O"
> boards, but only at DSP sampling rates of 200kHz or so. These are
> typically serial interfaces like I2S, so the data rate is on the order
> of 9 MHz or less. It will also likely need to configure/update various
> peripheral boards (command the DDS/Synthesizer(s), set gains, etc) but
> this is likely to be done using I2C or SPI style interfaces.
> Hopefully, LVDS won't be required for any of this.
> Lyle KK7P
I would be just as happy if we forgot about LVDS on the backplane. If
we need to deal with a high freq. clock (> 20 MHz ???) we can LVDS it
to a two pin header (or something) and use twisted pair to run it to
Can we get by with a two layer backplane - ground plane on top,
signal/power on bottom?
The LTC2208 Mercury board's initial mode will be to output serial I2S
data at <= 250 kSPS to the FPGA/USB or DSP board, so I don't need bus
speeds much over 10 MHz either.
73 de Phil C