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Re: [Xylo-SDR] Fundamental Atlas design decisions
That is the easiest and safest route to move a high frequency clock
around, twisted pair, and .1 Berg connectors are cheap. This is what I
have proposed since day one because LVDS on the back-plane is much
trickier to use, and if all we need is a couple of signals, then why
bother with the more complicated way.
At 12:28 PM 2/22/2006, you wrote:
On 2/22/06, Lyle Johnson
> > Question:
> > If the DSP board proposed
by Lyle were to be used is it
> > envisioned that it would be sitting on the
LVDS buss? If so would
> > it be listen only or would it drive the buss at times
> Depends entirely on what the I/O requirements are for the other
> The DSP board needs to communicate with the audio I/O
and "IF I/O"
> boards, but only at DSP sampling rates of 200kHz or so. These
> typically serial interfaces like I2S, so the data rate is on the
> of 9 MHz or less. It will also likely need to configure/update
> peripheral boards (command the DDS/Synthesizer(s), set gains, etc)
> this is likely to be done using I2C or SPI style interfaces.
> Hopefully, LVDS won't be required for any of this.
> Lyle KK7P
I would be just as happy if we forgot about LVDS on the backplane.
we need to deal with a high freq. clock (> 20 MHz ???) we can LVDS
to a two pin header (or something) and use twisted pair to run it to
Can we get by with a two layer backplane - ground plane on top,
signal/power on bottom?
The LTC2208 Mercury board's initial mode will be to output serial
data at <= 250 kSPS to the FPGA/USB or DSP board, so I don't need
speeds much over 10 MHz either.
73 de Phil C
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I fail to see why doing the same thing over and over and getting the
same results every time is insanity: I've almost proved it isn't; only a
few more tests now and I'm sure results will differ this time ...