Metis (formerly called Ozy II) - interface module
About the Metis Module
The project leader for the Metis board is Phil Harman, VK6APH
Metis will be a high speed PC PHY ethernet interface. Whilst the original Ozy board has served us well to date, in order to implement some of the future HPSDR projects we are going to need a faster interface between the various boards on the Atlas bus and the PC.
Aussie II is a kick off point for this project. Since this board will not need to support the SDR1000 there will be room for testing other high performance/speed interfaces.
Initial thoughts are around an Atlas size board that contains a large, leaded, Altera Cyclone III FPGA connected to a Gigabit Ethernet PHY.
User input relating to the design and features is requested via the HPSDR reflector.
Link to Wiki
Our HPSDR Wiki will contain the latest news, links, files, etc. for Magister. Here is the direct link to the HPSDR Wiki: Metis
Link to Documents
Here is the direct link to the Metis Documents: