High Performance Software Defined Radio

An Open Source Design


License NCL
Author Phil, VK6APH
Available from TAPR


December 23, 2010 Metis order page open at TAPR.

September 3, 2010 Board has moved to Beta testing.

September 3, 2010 Board Name changed from OzyII to Metis.

November 21, 2009 Prototype board is working!

Metis (formerly called Ozy II) - interface module

Metis module

About the Metis Module

The project leader for the Metis board is Phil Harman, VK6APH

Metis will be a high speed PC PHY ethernet interface. Whilst the original Ozy board has served us well to date, in order to implement some of the future HPSDR projects we are going to need a faster interface between the various boards on the Atlas bus and the PC.

Aussie II is a kick off point for this project. Since this board will not need to support the SDR1000 there will be room for testing other high performance/speed interfaces.

Initial thoughts are around an Atlas size board that contains a large, leaded, Altera Cyclone III FPGA connected to a Gigabit Ethernet PHY.

User input relating to the design and features is requested via the HPSDR reflector.

Link to Wiki

Our HPSDR Wiki will contain the latest news, links, files, etc. for Magister. Here is the direct link to the HPSDR Wiki: Metis

Link to Documents

Here is the direct link to the Metis Documents:

Support Documents

Metis Alpha board